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DESCRIPTION
The WM8983 is a low power, high quality stereo codec designed for portable multimedia applications. Highly flexible analogue mixing functions enable new application features, combining hi-fi quality audio with voice communication. The device integrates preamps for stereo differential mics, and includes drivers for speaker, headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal Automatic Level Control for the microphone or line input through the ADC as well as a purely digital limiter function for record or playback. A programmable high pass filter in the ADC path is provided for wind noise reduction and an IIR with programmable coefficients can be used as a notch filter to suppress fixed-frequency noise. The WM8983 digital audio interface can operate in master or slave mode, while an integrated PLL supports flexible clocking schemes. A-law and -law companding are fully supported. The WM8983 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. Speaker supplies can operate up to 5V for increased speaker output power. Additional power management control enables individual sections of the chip to be powered down under software control.
WM8983
Mobile Multimedia CODEC with 1W Speaker Driver
FEATURES
Stereo Codec: * DAC SNR 98dB, THD -84dB (`A' weighted @ 48kHz) * ADC SNR 95dB, THD -84dB (`A' weighted @ 48kHz) * Speaker driver (1W into 8 BTL with 5V supply) * Headphone driver with `capless' option * 40mW per channel output power into 16 / 3.3V AVDD2 * Pop and click suppression Mic Preamps: * Stereo Differential or mono microphone Interfaces * Programmable preamp gain * Psuedo differential inputs with common mode rejection * Programmable ALC / Noise Gate in ADC path * Low-noise bias supplied for electret microphones Other Features: * Enhanced 3-D function for improved stereo separation * Highly flexible mixing functions * 5-band equaliser (ADC or DAC path) * ADC Programmable high pass filter (wind noise reduction) * ADC Programmable IIR notch filter * Aux inputs for stereo analog input signals or `beep' * PLL supporting various clocks between 8MHz-50MHz * Sample rates supported (kHz): 8, 11.025, 16, 12, 16, 22.05, 24, 32, 44.1, 48 * 2.5V to 3.6V analogue supplies * 1.71V to 3.6V digital supplies * 2.5V to 5.5V speaker supplies * 5x5mm 32-pin QFN package
APPLICATIONS
* Multimedia phone
WOLFSON MICROELECTRONICS plc
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Product Preview, August 2005, Rev 1.1
Copyright 2005 Wolfson Microelectronics plc
WM8983 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 9
SPEAKER OUTPUT THD VERSUS POWER ......................................................10 POWER CONSUMPTION ....................................................................................11
TYPICAL SCENARIOS................................................................................................ 11
AUDIO PATHS OVERVIEW .................................................................................12 SIGNAL TIMING REQUIREMENTS .....................................................................13
SYSTEM CLOCK TIMING ........................................................................................... 13 AUDIO INTERFACE TIMING - MASTER MODE ........................................................ 13 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 14 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 15 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 16
INTERNAL POWER ON RESET CIRCUIT ..........................................................17 DEVICE DESCRIPTION.......................................................................................19
INTRODUCTION ......................................................................................................... 19 INPUT SIGNAL PATH ................................................................................................. 21 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 29 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 33 OUTPUT SIGNAL PATH ............................................................................................. 38 3D STEREO ENHANCEMENT .................................................................................... 45 ANALOGUE OUTPUTS............................................................................................... 45 DIGITAL AUDIO INTERFACES................................................................................... 62 AUDIO SAMPLE RATES ............................................................................................. 69 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 69 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 72 OUTPUT SWITCHING (JACK DETECT)..................................................................... 72 CONTROL INTERFACE.............................................................................................. 74 RESETTING THE CHIP .............................................................................................. 75 POWER SUPPLIES .................................................................................................... 75 POWER MANAGEMENT ............................................................................................ 75
REGISTER MAP...................................................................................................77 DIGITAL FILTER CHARACTERISTICS ...............................................................79
TERMINOLOGY .......................................................................................................... 79 DAC FILTER RESPONSES......................................................................................... 80 ADC FILTER RESPONSES......................................................................................... 80 HIGHPASS FILTER..................................................................................................... 81 5-BAND EQUALISER .................................................................................................. 82
APPLICATIONS INFORMATION .........................................................................86
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 86
IMPORTANT NOTICE ..........................................................................................88
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WM8983
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE WM8983GEFL WM8983GEFL/R Note: Reel quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 32-pin QFN (5 x 5 mm) (lead free) 32-pin QFN (5 x 5 mm) (lead free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM8983 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME LIP LIN L2/GPIO2 RIP RIN R2/GPIO3 LRC BCLK ADCDAT DACDAT MCLK DGND DCVDD DBVDD CSB/GPIO1 SCLK SDIN MODE AUXL AUXR OUT4 OUT3 ROUT2 AGND2 LOUT2 AVDD2 VMID AGND1 ROUT1 LOUT1 AVDD1 MICBIAS TYPE Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Digital Input / Output Digital Input / Output Digital Output Digital Input Digital Input Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Input Analogue input Analogue input Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Reference Supply Analogue Output Analogue Output Supply Analogue Output DESCRIPTION Left MIC pre-amp positive input Left MIC pre-amp negative input
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Left channel line input/secondary mic pre-amp positive input/GPIO2 pin Right MIC pre-amp positive input Right MIC pre-amp negative input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin DAC and ADC sample rate clock Digital audio bit clock ADC digital audio data output DAC digital audio data input Master clock input Digital ground Digital core logic supply Digital buffer (I/O) supply 3-Wire control interface chip Select / GPIO1 pin 3-Wire control interface clock input / 2-wire control interface clock input 3-Wire control interface data input / 2-Wire control interface data input Control interface selection Left auxillary input Right auxillary input right line output or mono mix output mono or left line output Headphone or line output right 2 Analogue ground (feeds ROUT2/LOUT2 and OUT3/OUT4) Headphone or line output left 2 Analogue supply (feeds output amplifiers ROUT2/LOUT2 and OUT3/OUT4) Decoupling for ADC and DAC reference voltage Analogue ground (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, ROUT1) Headphone or line output right 1 Headphone or line output left 1 Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, LOUT2)) Microphone bias
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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WM8983
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD1 supply voltages AVDD2 supply voltage Voltage range digital inputs Voltage range analogue inputs Storage temperature prior to soldering Storage temperature after soldering Notes 1. 2. 3. 4. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. Analogue supply voltages should not be less than digital supply voltages. In non-boosted mode AVDD2 should be AVDD1. In boost mode, AVDD2 should be 1.5 x AVDD1. MIN -0.3V -0.3V DGND -0.3V AGND1 -0.3V -65C MAX +3.63V +7V DVDD +0.3V AVDD1 +0.3V +150C
30C max / 85% RH max
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Speaker supply range Ground Notes 1. 2. Analogue supply voltages should not be less than digital supply voltages. DBVDD should be 1.9V when using the PLL. SYMBOL DCVDD DBVDD AVDD1 AVDD2 DGND, AGND1, AGND2 TEST CONDITIONS MIN 1.71 1.712 2.5 2.5 TYP 1.8 3.3 3.3 3.3 0 MAX 3.6 3.6 3.6 5.5 UNIT V V V V V
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WM8983 ELECTRICAL CHARACTERISTICS
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Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale Input Signal Level - single ended input configuration via L/RIN. Note1 Full-scale Input Signal Level - pseudo differential input configuration via L/RIP and L/R2. Note1 Mic PGA equivalent input noise Input resistance Input resistance Input resistance Input resistance Input resistance Input Capacitance Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost (0/+20dB) Gain Boost on PGA input Gain range from AUXL/R or L/R2 input to boost/mixer Gain step size to boost/mixer Auxilliary Analogue Inputs (AUXL, AUXR) Full-scale Input Signal Level (0dB) - note this is proportional to AVDD1 Input Resistance VINFS AVDD1/3.3 0 Left Input boost and mixer enabled, at max gain Left Input boost and mixer enabled, at 0dB gain Left Input boost and mixer enabled, at min gain Right Input boost, mixer and beep enabled, at max gain Right Input boost, mixer and beep enabled, at 0dB gain Right Input boost, mixer and beep enabled, at min gain 4.3 8.6 39.1 3 6 29 10 Vrms dBV k k k k k k pF Boost disabled Boost enabled -12 3 0 20 +6 dB dB dB dB Guaranteed monotonic SYMBOL VINFSSE TEST CONDITIONS PGABOOST = 0dB INPPGAVOL = 0dB PGABOOST = 0dB INPPGAVOL = 0dB MIN TYP 1.0 0 0.707 -3 MAX UNIT Vrms dBV Vrms dBV Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2)
VINFSPD
At 35.25dB gain RMICIN RMICIN RMICIN RMICIP RMICIP CMICIN
0 to 20kHz Gain set to 35.25dB Gain set to 0dB Gain set to -12dB RIP2INPPGA = 1 RIP2INPPGA = 0
150 1.6 47 75 90 90 10 -12 0.75 100 35.25
uV k k k k k pF dB dB dB
MIC Programmable Gain Amplifier (PGA)
RAUXINLMIN RAUXINLTYP RAUXINLMAX RAUXINRMIN RAUXINRTYP RAUXINRMAX
Input Capacitance Automatic Level Control (ALC) Target Record Level Programmable gain
CMICIN
-22.5 -12
-1.5 35.25
dB
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WM8983
Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Gain Hold Time (Note 2,4) Gain Ramp-Up (Decay) Time (Note 3,4) SYMBOL tHOLD tDCY TEST CONDITIONS MCLK = 12.288MHz (Note 2) ALCMODE=0 (ALC), MCLK=12.288MHz (Note 2) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 2) Gain Ramp-Down (Attack) Time (Note 3,4) tATK ALCMODE=0 (ALC), MCLK=12.288MHz (Note 2) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 2) Mute Attenuation Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 5,6) Total Harmonic Distortion (Note 7) Channel Separation (Note 8) Full-scale output Signal to Noise Ratio (Note 5,6) Signal to Noise Ratio (Note 5,6) Total Harmonic Distortion (Note 7) Channel Separation (Note 8) Output Mixers (LMX1, RMX1) PGA gain range into mixer PGA gain step into mixer Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2) Programmable Gain range Programmable Gain step size Mute attenuation 0dB full scale output voltage Signal to Noise Ratio Total Harmonic Distortion SNR THD Monotonic 1kHz, full scale signal With > 32R load A-weighted RL = 16, Po=20mW AVDD1=3.3V RL = 32 , Po=20mW AVDD1=3.3V Headphone Output (DAC to L/RMIX to LOUT1, ROUT1 with 16 load) Signal to Noise Ratio Signal to Noise Ratio SNR SNR A-weighted 22Hz to 20kHz 90 TBD dB dB -57 0 1 85 AVDD1/3.3 102 0.003 -92 0.008 - 82 +6 dB dB dB Vrms dB % dB % dB -15 0 3 +6 dB dB SNR SNR THD A-weighted, 0dB gain full-scale, 0dB gain 1kHz input signal PGA gains set to 0dB A-weighted 22Hz to 20kHz RL = 10k full-scale signal 1kHz signal 80 95 95 -84 110 AVDD1/3.3 98 95.5 -84 110 dB dB dB Vrms dB dB dB dB MIN TYP MAX UNIT ms ms 0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 3.3, 6.6, 13.1, ... , 3360 (time doubles with each step) 0.73, 1.45, 2.91, ... , 744 (time doubles with each step) 0.83, 1.66, 3.33, ... , 852 (time doubles with each step) 0.18, 0.36, 0.73, ... , 186 (time doubles with each step) 80dB dB ms
Digital to Analogue Converter (DAC) to L/R Mix to Line-Out (LOUT1, ROUT1 with 10k / 50pF load)
Headphone Output (AUX to L/RMIX to LOUT1, ROUT1. LOUT2, ROUT2 with 32 load)
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WM8983
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Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full scale output voltage, 0dB gain. (Note 9) SYMBOL TEST CONDITIONS SPKBOOST=0 SPKBOOST=1 Output Power Total Harmonic Distortion PO THD MIN TYP AVDD2/ 3.3 (AVDD2/ 3.3)*1.5 0.04 -68 1.0 -40 0.02 -74 1.0 -40 90 90 80 69 TBD TBD % dB % dB % dB % dB dB dB dB dB uA MAX UNIT Vrms Speaker Output (LOUT2, ROUT2 with 8 bridge tied load, INVROUT2=1)
Output power is very closely correlated with THD; see below PO =200mW, RL = 8, AVDD2=3.3V PO =320mW, RL = 8, AVDD2=3.3V PO =500mW, RL = 8, AVDD2=5V PO =860mW, RL = 8, AVDD2=5V
Signal to Noise Ratio
SNR
AVDD2=3.3V, RL = 8 AVDD2=5V, RL = 8
Power Supply Rejection Ratio (50Hz-22kHz) SPKVDD Leakage Current
PSRR
RL = 8 BTL RL = 8 BTL AVDD2=5V (boost) AVDD2 = 5V Other supplies disconnected AVDD2 = 5V Other supplies = 0V
OUT3/OUT4 outputs (with 10k / 50pF load) Full-scale output voltage, 0dB gain (Note 9) OUT3BOOST=0/ OUT4BOOST=0 OUT3BOOST=1/ OUT4BOOST=1 Signal to Noise Ratio (Note 5,6) Signal to Noise Ratio Total Harmonic Distortion (Note 7) Channel Separation (Note 8) Power Supply Rejection Ratio (50Hz-22kHz) Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input capacitance Input leakage VIH VIL VOH VOL IOL=1mA IOH-1mA TBD TBD 0.9xDBV DD 0.1xDBVDD 0.7xDBV DD 0.3xDBVDD V V V V pF pA VMICBIAS IMICBIAS Vn MBVSEL=0 MBVSEL=1 for VMICBIAS within +/-3% 1kHz to 20kHz 15 0.9*AVDD1 0.65*AVDD1 3 V V mA nV/Hz PSRR SNR SNR THD A-weighted 22Hz to 22kHz RL = 10 k full-scale signal 1kHz signal RL = 10k RL = 10k, AVDD2=5V 80 AVDD2/3.3 1.5 x AVDD2/3.3 98 97.5 -84 100 52 56 Vrms Vrms dB dB dB dB dB dB
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WM8983
TERMINOLOGY
1. 2. 3. 4. 5. 6. Note the full scale input level is proportional to AVDD1 and so will scale accordingly. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. The maximum output voltage can be limited by the speaker power supply. If SPKBOOST is set then AVDD2 should be 1.5xAVDD to prevent clipping taking place in the output stage (when PGA gains are set to 0dB).
7. 8. 9.
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WM8983 SPEAKER OUTPUT THD VERSUS POWER
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Figure 1 Speaker THD+N vs Output Power (Non-Boost Mode: SPKVDD=3.3V; SPKBOOST=0)
Figure 2 Speaker THD+N vs Output Power (Boost Mode: SPKVDD=5V; SPKBOOST=1)
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WM8983
POWER CONSUMPTION
TYPICAL SCENARIOS
Estimated current consumption for typical scenarios are shown below. Power delivered to the load is not included. MODE Off (No clocks, temperature sensor disabled) Sleep (VREF maintained) Mono Record from Differential MIC (8kHz, PLL enabled) Stereo HP Playback (44.1kHz, PLL enabled) Table 1 Power Consumption IAVDD1 mA (3.3V) 0.010 0.100 4.000 3.700 IAVDD2 mA (3.3V) 0.010 0.001 0.001 0.950 IDCVDD mA (1.8V) 0.001 0.012 0.400 2.100 IDBVDD mA (1.8V) 0.002 0.003 0.030 0.100 TOTAL mW 0.071 0.360 13.97 19.31
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WM8983 AUDIO PATHS OVERVIEW
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WM8983
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 3 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25oC, Slave Mode PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note: 1. PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. TMCLKY TMCLKDS MCLK=SYSCLK (=256fs) MCLK input to PLL Note 1 81.38 20 60:40 40:60 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 4 Digital Audio Data Timing - Master Mode (see Control Interface)
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WM8983
Test Conditions
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DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 5 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from BCLK rising edge DACDAT hold time from BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDD 50 20 20 10 10 10 10 ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8983
CONTROL INTERFACE TIMING - 3-WIRE MODE
3-wire mode is selected by connecting the MODE pin high.
Figure 6 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
o
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WM8983
CONTROL INTERFACE TIMING - 2-WIRE MODE
2-wire mode is selected by connecting the MODE pin low.
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
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t8
Figure 7 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns DGND=AGND1=AGND2=0V, SYMBOL TA=+25oC, MIN Slave TYP Mode, MAX fs=48kHz, UNIT
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WM8983
INTERNAL POWER ON RESET CIRCUIT
Figure 8 Internal Power on Reset Circuit Schematic The WM8983 includes an internal Power-On-Reset Circuit, as shown in Figure 8, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.
Figure 9 Typical Power up Sequence Where AVDD1 is Powered Before DCVDD
Figure 9 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the minimum threshold Vpora_off.
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WM8983
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Figure 10 Typical Power up Sequence Where DCVDD is Powered Before AVDD1 Figure 10 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1 rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off.
SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off
MIN 0.4 0.9 0.4 0.5 0.4
TYP 0.6 1.2 0.6 0.7 0.6
MAX 0.8 1.6 0.8 0.9 0.8
UNIT V V V V V
Table 2 Typical POR Operation (typical values, not tested) Notes: 1. If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This specification is guaranteed by design rather than test.
2.
3.
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WM8983
DEVICE DESCRIPTION
INTRODUCTION
The WM8983 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain. The provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip which can be used to bias both microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
LINE INPUTS (AUXL, AUXR)
AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or `beeps') etc. These inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with `backing music' etc as required.
ADC
The stereo ADC uses a 24-bit high-order oversampling architecture to deliver optimum performance with low power consumption.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players, portable multimedia devices and portable disc players of all types.
OUTPUT MIXERS
Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow for all possible signal combinations.
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Product Preview OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo differential inputs to external amplifiers.
AUDIO INTERFACES
The WM8983 has a standard audio interface, to support the transmission of stereo data to and from the chip. This interface is a 3 wire standard audio interface which supports a number of audio data formats including: * * * * IS DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are transmitted) MSB-First, left justified MSB-First, right justified
2
The interface can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all features, the WM8983 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8983 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller. This PLL can accept a range of common input clock frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the GPIO pins and used elsewhere in the system.
POWER CONTROL
The design of the WM8983 has given much attention to power consumption without compromising performance. It operates at very low voltages, includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes.
AUXILIARY ANALOG INPUT SUPPORT
Additional stereo analog signals might be connected to the Line inputs of WM8983 (e.g. melody chip or FM radio), and the stereo signal listened to via headphones, or recorded, simultaneously if required.
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WM8983
INPUT SIGNAL PATH
The WM8983 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers.
MICROPHONE INPUTS
The WM8983 can accommodate a variety of microphone configurations including single ended and pseudo differential inputs. The inputs to the left pseudo differential input PGA are LIP and L2. The inputs to the right pseudo differential input PGA are RIP and R2. LIN and RIN are used for a.c. coupled ground inputs. In single-ended microphone input configuration the microphone signal should be input to LIN or RIN and the non-inverting input of the input PGA clamped to VMID.
Figure 11 Microphone Input PGA Circuit
The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPPGAENL DEFAULT 0 DESCRIPTION Left channel input PGA enable 0 = disabled 1 = enabled Right channel input PGA enable 0 = disabled 1 = enabled
3
INPPGAENR
0
Table 3 Input PGA Enable Register Settings
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REGISTER ADDRESS R44 Input Control
BIT 0
LABEL LIP2INPPGA
DEFAULT 1
DESCRIPTION Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) Connect LIN pin to left channel input PGA negative terminal. 0 = LIN not connected to input PGA 1 = LIN connected to input PGA amplifier negative terminal. Connect L2 pin to left channel input PGA positive terminal. 0 = L2 not connected to input PGA 1 = L2 connected to input PGA amplifier positive terminal (constant input impedance). Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Connect RIN pin to right channel input PGA negative terminal. 0 = RIN not connected to input PGA 1 = RIN connected to right channel input PGA amplifier negative terminal. Connect R2 pin to right channel input PGA positive terminal. 0 = R2 not connected to input PGA 1 = R2 connected to input PGA amplifier positive terminal (constant input impedance).
1
LIN2INPPGA
1
2
L2_2INPPGA
0
4
RIP2INPPGA
1
5
RIN2INPPGA
1
6
R2_2INPPGA
0
Table 4 Input PGA Control
INPUT PGA VOLUME CONTROLS
The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also affect the LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1 and the L2 pin when L2_2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the INPPGAVOLL/R bits should not be used.
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WM8983
REGISTER ADDRESS R45 Left channel input PGA volume control BIT 5:0 LABEL INPPGAVOLL DEFAULT 010000 DESCRIPTION Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). Left channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Mute control for right channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). Right channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) ALC function select: 00 = ALC off 01 = ALC right only 10 = ALC left only 11 = ALC both on
6
INPPGAMUTEL
0
7
INPPGAZCL
0
8
INPPGAVU
Not latched
R46 Right channel input PGA volume control
5:0
INPPGAVOLR
010000
6
INPPGAMUTER
0
7
INPPGAZCR
0
8
INPPGAVU
Not latched
R32 ALC control 1
8:7
ALCSEL
00
Table 5 Input PGA Volume Control
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VOLUME UPDATES
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Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 12.
Figure 12 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 13.
Figure 13 Click Noise During Volume Update In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause the PGA volume to update only when a zero crossing occurs, minimising click noise as shown in Figure 14.
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Figure 14 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8983 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAVU bit is set as shown in Figure 15.
Figure 15 Volume Update after Timeout
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AUXILLIARY INPUTS
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There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a `beep' input signal to be mixed with the outputs. As signal inputs, AUXL/R inputs can be used as a line input to the input BOOST stage which has adjustable gain of -12dB to +6dB in 3dB steps, with an additional "off" state (i.e. not connected to ADC input). See the INPUT BOOST section for further details. The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off.
INPUT BOOST
Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 16.
Figure 16 Input Boost Stage The input PGA paths can have a +20dB boost (PGABOOSTL/R=1) , a 0dB pass through (PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1).
REGISTER ADDRESS R47 Left Input BOOST control
BIT 8
LABEL PGABOOSTL
DEFAULT 1
DESCRIPTION Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
R48 Right Input BOOST control
8
PGABOOSTR
1
Table 6 Input BOOST Stage Control The Auxilliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL/R2_2BOOSTVOL=000 the L2/R2 input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
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WM8983
REGISTER ADDRESS R42 OUT4 to ADC BIT 8:6 LABEL OUT4_2ADCVOL DEFAULT 000 DESCRIPTION Controls the OUT4 to ADC input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input Controls the auxiliary amplifier to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the auxiliary amplifier to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
5
OUT4_2LNR
0
R47 Left channel Input BOOST control
2:0
AUXL2BOOSTVOL
000
6:4
L2_2BOOSTVOL
000
R48 Right channel Input BOOST control
2:0
AUXR2BOOSTVOL
000
6:4
R2_2BOOSTVOL
000
Table 7 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit.
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REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTENL DEFAULT 0
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5
BOOSTENR
0
Table 8 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1, MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 Power management 1 BIT 4 LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 9 Microphone Bias Enable Control
REGISTER ADDRESS R44 Input control
BIT 8
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1
Table 10 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 17. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
VMID internal resistor
MICBEN MICBIAS
MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD1 MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD1
internal resistor
AGND1
Figure 17 Microphone Bias Schematic
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WM8983
The WM8983 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ANALOGUE TO DIGITAL CONVERTER (ADC)
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path for each ADC channel is illustrated in Figure 18.
Figure 18 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS R2 Power management 2 BIT 0 LABEL ADCENL DEFAULT 0 DESCRIPTION Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled
1
ADCENR
0
Table 11 ADC Enable Control The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 ADC Control BIT 0 LABEL ADCLPOL DEFAULT 0 DESCRIPTION ADC left channel polarity adjust: 0 = normal 1 = inverted ADC right channel polarity adjust: 0 = normal 1 = inverted ADC oversample rate select: 0 = 64x (lower power) 1 = 128x (best performance)
1
ADCRPOL
0
3
ADCOSR
0
Table 12 ADC Control
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SELECTABLE HIGH PASS FILTER
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A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14. REGISTER ADDRESS R14 ADC Control 8 BIT LABEL HPFEN DEFAULT 1 DESCRIPTION High Pass Filter Enable 0 = disabled 1 = enabled Select audio mode or application mode 0 = Audio mode (1st order, fc = ~3.7Hz) 1 = Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 14 for details.
7
HPFAPP
0
6:4
HPFCUT
000
Table 13 ADC Enable Control
HPFCUT [2:0] 8 000 001 010 011 100 101 110 111 82 102 131 163 204 261 327 408
SR=101/100 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408
SR=011/010 fs (kHz) 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408
SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 14.
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WM8983
PROGRAMMABLE IIR NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS R27 Notch Filter 1 7 BIT 6:0 LABEL NFA0[13:7] NFEN DEFAULT 0 0 DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0 = Disabled 1 = Enabled Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high.
8
NFU
0
R28 Notch Filter 2
6:0 8
NFA0[6:0] NFU
0 0
R29 Notch Filter 3
6:0 8
NFA1[13:7] NFU
0 0
R30 Notch Filter 4
0-6 8
NFA1[6:0] NFU
0 0
Table 15 Notch Filter Function The coefficients are calculated as follows:
a0 =
1 - tan( wb / 2) 1 + tan( wb / 2)
a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 x (G-255) dB for 1 G 255; MUTE for G = 0
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REGISTER ADDRESS R15 Left channel ADC Digital Volume BIT 7:0 LABEL ADCLVOL [7:0] DEFAULT 11111111 ( 0dB )
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DESCRIPTION Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16)
8
ADCVU
Not latched 11111111 ( 0dB )
R16 Right channel ADC Digital Volume
7:0
ADCRVOL [7:0]
8
ADCVU
Not latched
Table 16 ADC Digital Volume Control
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WM8983
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8983 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its static level.
Figure 19 Input Peak Limiter Operation In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
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Figure 20 ALC Operation The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the recording volume can be programmed between -6dB and -28.5dB (relative to ADC full scale) using the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits. ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a time per gain step, time per 6dB change and time to ramp up over 90% of it's range. The decay n time can be programmed in power-of-two (2 ) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc. to 3.36s/6dB. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given as a time per gain step, time per 6dB change and time to ramp down over 90% of it's range. The attack time can be programmed in power-of-two (2n) steps, from 832us/6dB, 1.66ms/6dB, 3.328us/6dB, etc. to 852ms/6dB. NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. Attack and Decay times for peak limiter mode are given below. The hold, decay and attack times given in Table 17 are constant across sample rates so long as the SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 17 will only be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the hold, decay and attack times would be scaled down by 44.1/48. Note: Zero cross function can affect these time constants, and is not recommended for use during ALC operation.
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WM8983
REGISTER ADDRESS R32 ALC Control 1
BIT 8:7
LABEL ALCSEL
DEFAULT 00
DESCRIPTION ALC function select 00 = ALC disabled 01 = Right channel ALC enabled 10 = Left channel ALC enabled 11 = Both channels ALC enabled Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS ...... (-1.5dB steps) 0001 = -21dBFS 0000 = -22.5dBFS ALC uses zero cross detection circuit. (not recommended for use with ALC)
5:3
ALCMAXGAIN [2:0]
111 (+35.25dB)
2:0
ALCMINGAIN [2:0]
000 (-12dB)
R33 ALC Control 2
7:4
ALCHLD [3:0]
0000 (0ms)
3:0
ALCLVL [3:0]
1011 (-12dB)
8
ALCZC
0 (zero cross off)
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R34 ALC Control 3 8 ALCMODE 0
Product Preview Determines the ALC mode of operation: 0 = ALC mode 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 1010 or higher 0011 (2.9ms/6dB) 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
7:4
ALCDCY [3:0]
0011 (13ms/6dB)
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 90.8us 181.6us 363.2us Per 6dB 726.4us 1.453 ms 2.905 ms 744ms 90% of range 5.26ms 10.53 ms 21.06 ms 5.39s
... (time doubles with every step) 1010 3:0 ALCATK [3:0] 0010 (832us/6dB) 93ms ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 104us 208us 416us Per 6dB 832us 1.664 ms 3.328 ms 852ms 90% of range 6ms 12ms 24.1ms
... (time doubles with every step) 1010 or higher 0010 (182us/6dB) 106ms 6.18s
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s
... (time doubles with every step) Table 17 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
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WM8983
MINIMUM AND MAXIMUM GAIN
The ALCMINGAIN and ALCMAXGAIN register sets the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8983 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS R35 ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db ... (6dB steps) 111 = -81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 18 ALC Noise Gate Control
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OUTPUT SIGNAL PATH
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The WM8983 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL And DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8983, irrespective of whether the DACs are running or not. The WM8983 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: * Digital volume control * Graphic equaliser * A digital peak limiter. * Sigma-Delta Modulation High performance sigma-delta audio DAC converts the digital data into an analogue signal.
Figure 21 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them to output different signals to the headphone and line outputs.
DIGITAL PLAYBACK (DAC) PATH
Digital data is passed to the WM8983 via the flexible audio interface and is then passed through a variety of advanced digital filters as shown in Figure 21 to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits. REGISTER ADDRESS R3 Power Management 3 BIT 0 LABEL DACENL DEFAULT 0 DESCRIPTION Left channel DAC enable 0 = DAC disabled 1 = DAC enabled Right channel DAC enable 0 = DAC disabled 1 = DAC enabled
1
DACENR
0
Table 19 DAC Enable Control The WM8983 also has a Soft Mute function, which when enabled, gradually attenuates the volume of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the SOFTMUTE bit to zero.
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WM8983
REGISTER ADDRESS R10 DAC Control BIT 0 LABEL DACPOL DEFAULT 0 DESCRIPTION Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) Automute enable 0 = Amute disabled 1 = Amute enabled DAC oversampling rate: 0 = 64x (lowest power) 1 = 128x (best performance) Softmute enable: 0 = Enabled 1 = Disabled
1
DACRPOL
0
2
AMUTE
0
3
DACOSR
0
6
SOFTMUTE
0
Table 20 DAC Control Register The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase on the left channel and DACRPOL inverts the phase on the right channel.
AUTO-MUTE
The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be disabled using the AMUTE control bit.
DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; MUTE for X = 0
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REGISTER ADDRESS R11 Left DAC Digital Volume BIT 7:0 LABEL DACLVOL [7:0] DEFAULT 11111111 ( 0dB )
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DESCRIPTION Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12)
8
DACVU
Not latched 11111111 ( 0dB )
R12 Right DAC Digital Volume
7:0
DACRVOL [7:0]
8
DACVU
Not latched
Table 21 DAC Digital Volume Control Note: An additional gain of up to 12dB can be added using the gain block embedded in the digital peak limiter circuit (see DAC OUTPUT LIMITER section).
5-BAND EQUALISER
A 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND EQUALISER section for further details on this feature.
3-D ENHANCEMENT
The WM8983 has an advanced digital 3-D enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can be applied to either the ADC record path or the DAC plaback path but not both simultaneously. Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature.
DAC DIGITAL OUTPUT LIMITER
The WM8983 has a digital output limiter function. The operation of this is shown in Figure 22. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
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WM8983
Figure 22 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 22, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
VOLUME BOOST
The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
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REGISTER ADDRESS R24 DAC digital limiter control 1 BIT 3:0 LABEL LIMATK DEFAULT 0010
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DESCRIPTION Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate. 0000 = 94us 0001 = 188s 0010 = 375us 0011 = 750us 0100 = 1.5ms 0101 = 3ms 0110 = 6ms 0111 = 12ms 1000 = 24ms 1001 = 48ms 1010 = 96ms 1011 to 1111 = 192ms Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate: 0000 = 750us 0001 = 1.5ms 0010 = 3ms 0011 = 6ms 0100 = 12ms 0101 = 24ms 0110 = 48ms 0111 = 96ms 1000 = 192ms 1001 = 384ms 1010 = 768ms 1011 to 1111 = 1.536s Enable the DAC digital limiter: 0 = disabled 1 = enabled Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved Programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1dB 001 = -2dB 010 = -3dB 011 = -4dB 100 = -5dB 101 to 111 = -6dB
7:4
LIMDCY
0011
8
LIMEN
0
R25 DAC digital limiter control 2
3:0
LIMBOOST
0000
6:4
LIMLVL
000
Table 22 DAC Digital Limiter Control
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WM8983
5-BAND GRAPHIC EQUALISER
A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. The ADCs and DACs should be disabled before changing the AQ3DMODE bit. REGISTER ADDRESS R18 EQ Control 1 BIT 8 LABEL EQ3DMODE DEFAULT 1 DESCRIPTION 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path
Table 23 EQ and 3D Enhancement DAC or ADC Path Select
The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER ADDRESS R18 EQ Band 1 Control
BIT 4:0 6:5
LABEL EQ1G EQ1C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 1 Gain Control. See Table 29 for details. Band 1 Cut-off Frequency: 00 = 80Hz 01 = 105Hz 10 = 135Hz 11 = 175Hz
Table 24 EQ Band 1 Control
REGISTER ADDRESS R19 EQ Band 2 Control
BIT 4:0 6:5
LABEL EQ2G EQ2C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 2 Gain Control. See Table 29 for details. Band 2 Centre Frequency: 00 = 230Hz 01 = 300Hz 10 = 385Hz 11 = 500Hz Band 2 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ2BW
0
Table 25 EQ Band 2 Control
REGISTER ADDRESS R20 EQ Band 3 Control
BIT 4:0 6:5
LABEL EQ3G EQ3C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 3 Gain Control. See Table 29 for details. Band 3 Centre Frequency: 00 = 650Hz 01 = 850Hz 10 = 1.1kHz 11 = 1.4kHz Band 3 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ3BW
0
Table 26 EQ Band 3 Control
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REGISTER ADDRESS R21 EQ Band 4 Control BIT 4:0 6:5 LABEL EQ4G EQ4C DEFAULT 01100 (0dB) 01
Product Preview DESCRIPTION Band 4 Gain Control. See Table 29 for details Band 4 Centre Frequency: 00 = 1.8kHz 01 = 2.4kHz 10 = 3.2kHz 11 = 4.1kHz Band 4 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth
8
EQ4BW
0
Table 27 EQ Band 4 Control
REGISTER ADDRESS R22 EQ Band 5 Gain Control
BIT 4:0 6:5
LABEL EQ5G EQ5C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 5 Gain Control. See Table 29 for details. Band 5 Cut-off Frequency: 00 = 5.3kHz 01 = 6.9kHz 10 = 9kHz 11 = 11.7kHz
Table 28 EQ Band 5 Control
GAIN REGISTER 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 11000 11001 to 11111 Table 29 Gain Register Table
GAIN +12dB +11dB +10dB +9dB +8dB +7dB +6dB +5dB +4dB +3dB +2dB +1dB 0dB -1dB -12dB Reserved
See also Figure 51 to Figure 68 for equaliser and high pass filter responses.
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WM8983
3D STEREO ENHANCEMENT
The WM8983 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8983 control interface will only allow EQ3DMODE to be changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and DACENR = 0). The DEPTH3D setting controls the degree of stereo expansion. When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.
REGISTER ADDRESS R41 (29h) 3D Control
BIT 3:0
LABEL DEPTH3D[3:0]
DEFAULT 0000
DESCRIPTION Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% 0010: 13.33 0011: 20.00 0100: 26.67 0101: 33.33 0110: 40.0 0111: 46.67 1000: 53.33 1001: 60.00 1010: 66.67 1011: 73.33 1100: 80.00 1101: 86.67 1110: 93.3% 1111: 100% (maximum 3D effect)
Table 30 3D Stereo Enhancement Function
ANALOGUE OUTPUTS
The WM8983 has three sets of stereo analogue outputs. These are: * * * LOUT1 and ROUT1 which are normally used to drive a headphone load. LOUT2 and ROUT2 - which can be used as speaker, headphone or line drivers. OUT3 and OUT4 - can be configured as a stereo line out (OUT3 is left output and OUT4 is right output). OUT4 can also be used to provide a mono mix of left and right channels.
The outputs LOUT2, ROUT2 OUT3 and OUT4 are powered from AVDD2 and are capable of driving a 1V rms signal (AVDD1/3.3) in non-boost mode and AVDD1*1.5/3.3 in boost mode. LOUT1 and ROUT1 are supplied from AVDD1 and can drive out a 1V rms signal (AVDD1/3.3). LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB gain ranges. There are four output mixers in the output signal path, the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers.
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LEFT AND RIGHT OUTPUT CHANNEL MIXERS
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The left and right output channel mixers are shown in Figure 23. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be performed as well as mixing in external line-in from the AUX or speech from the input bypass path. The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be adjusted in the digital domain if required. The output of these mixers is connected to the headphone outputs (LOUT1, ROUT1, LOUT2 and ROUT2) and can optionally be connected to the OUT3 and OUT4 mixers.
Figure 23 Left/Right Output Channel Mixers
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WM8983
REGISTER ADDRESS R43 Output mixer control BIT 8 LABEL BYPL2RMIX DEFAULT 0 DESCRIPTION Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected Right DAC output to left output mixer 0 = not selected 1 = selected Left DAC output to right output mixer 0 = not selected 1 = selected Left DAC output to left output mixer 0 = not selected 1 = selected Left bypass path (from the left channel input PGA stage) to left output mixer 0 = not selected 1 = selected Left bypass volume contol to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB
R43 Output mixer control
7
BYPR2LMIX
0
R49 Output mixer control
5
DACR2LMIX
0
6
DACL2RMIX
0
R50 Left channel output mixer control
0
DACL2LMIX
1
1
BYPL2LMIX
0
4:2
BYPLMIXVOL
000
5
AUXL2LMIX
0
8:6
AUXLMIXVOL
000
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R51 Right channel output mixer control 0 DACR2RMIX 1
Product Preview Right DAC output to right output mixer 0 = not selected 1 = selected Right bypass path (from the right channel input PGA stage) to right output mixer 0 = not selected 1 = selected Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB Left output channel mixer enable: 0 = disabled 1 = enabled Right output channel mixer enable: 0 = disabled 1 = enabled
1
BYPR2RMIX
0
4:2
BYPRMIXVOL
000
5
AUXR2RMIX
0
8:6
AUXRMIXVOL
000
R3 Power management 3
2
LMIXEN
0
3
RMIXEN
0
Table 31 Left and Right Output Mixer Control
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WM8983
HEADPHONE OUTPUTS (LOUT1 AND ROUT1)
The headphone outputs LOUT1 and ROUT1 can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC-coupled to a buffered midrail reference as shown in Figure 24. OUT3, OUT4, LOUT2 or ROUT2 could be used as this buffered reference if one of these outputs is not being used, saving decoupling capacitors, at the expense of increased power consumption. For fully independent left and right channels, two separate midrail references can be used, eliminating crosstalk caused by headphone ground impedances, at the expense of increased power consumption.
Headphone Output using DC Blocking Capacitors:
Lowest power consumption (Two outputs enabled); Large and expensive capacitors; Bass response may be reduced for smaller capacitors; Impedance in common ground may introduce crosstalk.
DC Coupled Headphone Output:
Higher power consumption (Three outputs enabled); Improved PSRR if AVDD2 connected to AVDD1; Impedance in common ground may introduce crosstalk; Improved bass response (DC connection).
DC Coupled with Fully Independent Left / Right Drive: Highest power consumption (Four outputs enabled); Improved PSRR if AVDD2 connected to AVDD1; Independent L/R pseudo-ground eliminates crosstalk; Improved bass response (DC connection); Non-standard headphone connection may not be suitable for some applications.
Figure 24 Recommended Headphone Output Configurations Each headphone output has an analogue volume control PGA with a gain range of -57dB to +6dB. When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the VMID pin. The OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. Note that LOUT2, ROUT2, OUT3 and OUT4 have an optional output boost of 1.5x. When these are configured in this output boost mode (SPKBOOST/OUT3BOOST/OUT4BOOST=1) then the VMID value of these outputs will be equal to 1.5xAVDD/2 and will not match the VMID of the headphone drivers. Do not use the DC coupled output mode in this configuration. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
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REGISTER ADDRESS R52 LOUT1 Volume control BIT 7 LABEL LOUT1ZC DEFAULT 0
Product Preview DESCRIPTION Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left headphone output mute: 0 = Normal operation 1 = Mute Left headphone output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right headphone output mute: 0 = Normal operation 1 = Mute Right headphone output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53)
6
LOUT1MUTE
0
5:0
LOUT1VOL
111001
8
HPVU
Not latched
R53 ROUT1 Volume control
7
ROUT1ZC
0
6
ROUT1MUTE
0
5:0
ROUT1VOL
111001
8
HPVU
Not latched
Table 32 OUT1 Volume Control
SPEAKER OUTPUTS (LOUT2 AND ROUT2)
The outputs LOUT2 and ROUT2 are designed to drive an 8 BTL speaker but can optionally drive two headphone loads of 16/32 or a line output (see Headphone Output and Line Output sections, respectively). Each output has an individual volume control PGA, an output boost/level shift bit, a mute and an enable as shown in Figure 25. LOUT2 and ROUT2 output the left and right channel mixer outputs respectively. The ROUT2 signal path also has an optional invert. The amplifier used for this invert can be used to mix in the AUXR signal with an adjustable gain range of -15dB -> +6dB. This allows a `beep' signal to be applied only to the speaker output without affecting the HP or line outputs.
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WM8983
Figure 25 Speaker Outputs LOUT2 and ROUT2
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SPEAKER BOOST MODE
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To support speaker boost mode, AVDD2 should be at least 1.5*AVDD1. A higher AVDD2 will improve THD performance at the expense of power consumption while lower AVDD2 will cause clipping. Variations in AVDD1 and AVDD2 should be taken into account when using speaker boost mode as shown in Figure 26 and Figure 27.
Figure 26 Non-Boost Mode Output Operation
Figure 27 Boost Mode Output Operation
LOUT2 and ROUT2 outputs can be connected directly to a Lithium battery to improve THD performance in non-boost mode. Although direct battery connection is also possible in boost mode, the discharge characteristic of the battery can lead to clipping after a relatively short period of time as shown in Figure 28. Reducing the maximum permitted volume and keeping AVDD1 to a minimum will allow boost mode to operate for longer.
Figure 28 Output Boost Mode with Direct Battery Connection As the full scale output falls close to AVDD1, it becomes more effective to use non-boost mode to generate a louder output, although SPKBOOST should NOT be changed while the speaker output is driving out a signal. As a general rule: if AVDD2 - (AVDD1 * 0.75) > AVDD1 / 2 boost mode provides more power output; if AVDD2 - (AVDD1 * 0.75) < AVDD1 / 2 non-boost mode provides more power output.
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WM8983
REGISTER ADDRESS R54 LOUT2 Volume control
BIT 7
LABEL LOUT2ZC
DEFAULT 0
DESCRIPTION LOUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Left output mute: 0 = Normal operation 1 = Mute Left output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) ROUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Right output mute: 0 = Normal operation 1 = Mute Right output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55)
6
LOUT2MUTE
0
5:0
LOUT2VOL
111001
8
SPKVU
Not latched
R55 ROUT2 Volume control
7
ROUT2ZC
0
6
ROUT2MUTE
0
5:0
ROUT2VOL
111001
8
SPKVU
Not latched
Table 33 OUT2 Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the Bypass path (output of the input boost stage) and the AUX input. The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB may cause clipping if the signal is large. The LOUT2MUTE/ ROUT2MUTE register bits cause the speaker outputs to be muted (the output DC level is driven out). The output pins remain at the same DC level (DCOP), so that no click noise is produced when muting or un-muting The speaker output stages also have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD1/2 to 1.5xAVDD1/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 29, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if AVDD2 is not equal to or greater than 1.5xAVDD1 this boost mode may result in signals clipping. Table 35 summarises the effect of the SPKBOOST control bits.
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REGISTER ADDRESS R49 Output control BIT 2 LABEL SPKBOOST DEFAULT 0
Product Preview
DESCRIPTION 0 = speaker gain = -1; DC = AVDD1 / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD1 / 2 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0 = Buffer disabled 1 = Buffer enabled (required for 1.5x gain boost)
R1 Power management 1
8
BUFDCOPEN
0
Table 34 Speaker Boost Stage Control SPKBOOST 0 1 OUTPUT STAGE GAIN 1x (0dB) 1.5x (3.52dB) OUTPUT DC LEVEL AVDD1/2 1.5xAVDD1/2 OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 35 Output Boost Stage Details
REGISTER ADDRESS R43 Beep control
BIT 5 4 3:1
LABEL MUTERPGA2INV INVROUT2 BEEPVOL
DEFAULT 0 0 000
DESCRIPTION Mute input to INVROUT2 mixer Invert ROUT2 output AUXR input to ROUT2 inverter gain 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB 0 = mute AUXR beep input 1 = enable AUXR beep input
0
BEEPEN
0
Table 36 AUXR - ROUT2 BEEP Mixer Function
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * SYSCLK period. REGISTER ADDRESS R7 Additional Control BIT 0 LABEL SLOWCLKEN DEFAULT 0 DESCRIPTION Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled
Table 37 Timeout Clock Enable Control
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WM8983
OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 30. The OUT3 and OUT4 output stages are powered from AVDD2 and AGND2. These individuallycontrollable outputs also incorporate an optional 1.5x boost and level shifting stage.
Figure 30 OUT3 and OUT4 Mixers OUT3 can provide a midrail reference, a left line output, or a mono mix line output OUT4 can provide a midrail reference, a right line output, or a mono mix line output. A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right signals. This function is enabled by the OUT4ATTN register bit.
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REGISTER ADDRESS R56 OUT3 mixer control BIT 6 LABEL OUT3MUTE DEFAULT 0
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DESCRIPTION 0 = Output stage outputs OUT3 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID reference in this mode. OUT4 mixer output to OUT3 0 = disabled 1 = enabled Left ADC input to OUT3 0 = disabled 1 = enabled Left DAC mixer to OUT3 0 = disabled 1= enabled Left DAC output to OUT3 0 = disabled 1 = enabled OUT3 mixer output to OUT4 0 = disabled 1= enabled 0 = Output stage outputs OUT4 mixer 1 = Output stage muted - drives out VMID. Can be used as VMID reference in this mode. 0 = OUT4 normal output 1 = OUT4 attenuated by 6dB Left DAC mixer to OUT4 0 = disabled 1 = enabled Left DAC to OUT4 0 = disabled 1 = enabled Right ADC input to OUT4 0 = disabled 1 = enabled Right DAC mixer to OUT4 0 = disabled 1 = enabled Right DAC output to OUT4 0 = disabled 1 = enabled
3
OUT4_2OUT3
0
2
BYPL2OUT3
0
1
LMIX2OUT3
0
0
LDAC2OUT3
1
R57 OUT4 mixer control
7
OUT3_2OUT4
0
6
OUT4MUTE
0
5 4
OUT4ATTN LMIX2OUT4
0 0
3
LDAC2OUT4
0
2
BYPR2OUT4
0
1
RMIX2OUT4
0
0
RDAC2OUT4
1
Table 38 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD1/2 to 1.5xAVDD1/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 31, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if AVDD2 is not equal to or greater than 1.5xAVDD1 this boost mode may result in signals clipping. Table 35 summarises the effect of the OUT3BOOST and OUT4BOOST control bits.
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WM8983
Figure 32 Outputs OUT3 and OUT4
REGISTER ADDRESS R49 Output control
BIT 3
LABEL OUT3BOOST
DEFAULT 0
DESCRIPTION 0 = OUT3 output gain = -1; DC = AVDD1 / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD1 / 2 0 = OUT4 output gain = -1; DC = AVDD1 / 2 1 = OUT4 output gain = +1.5 DC = 1.5 x AVDD1 / 2 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost)
4
OUT4BOOST
0
R1 Power management 1
8
BUFDCOPEN
0
Table 39 OUT3 and OUT4 Boost Stages Control
OUT3BOOST/ OUT4BOOST 0 1
OUTPUT STAGE GAIN 1x 1.5x
OUTPUT DC LEVEL AVDD1/2 1.5xAVDD1/2
OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 40 OUT3 and OUT4 Output Boost Stage Details
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OUTPUT PHASING
The relative phases of the analogue outputs will depend upon the following factors:
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1. DACLPOL and DACRPOL invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal will depend upon the route through the mixer path. For example, DACL can be directly input to the OUT3 mixer, giving a 180 phase shift at the OUT3 mixer output. However, if DACL is input to the OUT3 mixer via the left mixer, an additional phase shift will be introduced, giving 0 phase shift at the OUT3 mixer output. 3. Output boost set-up: When 1.5x boost is enabled on an output, no phase shift occurs. When 1.5x boost is not enabled, a 180 phase shift occurs. Figure 23 shows where these phase inversions can occur in the output signal path.
Figure 33 Output Signal Path Phasing
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Product Preview Table 41 shows the polarities of the outputs in various configurations.
WM8983
Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings, output enables etc are not shown).
CONFIGURATION
MIXER PATH REGISTERS DIFFERENT FROM DEFAULT
DACLPOL 0
DACRPOL
INVROUT2
SPKBOOST
OUT3BOOST
OUT4BOOST
OUT4 PHASE / MAG
OUT3 PHASE / MAG
LOUT1 PHASE / MAG
ROUT1 PHASE / MAG
LOUT2 PHASE / MAG
ROUT2 PHASE / MAG 180 1
Default: Stereo DAC playback to LOUT1/ROUT1, LOUT2/ROUT2 and OUT4/OUT3 DACs inverted
0
0
0
0
0
0 1
0 1
0 1
0 1
180 1
1
1
0
0
0
0
180 1
180 1 0 1
180 1 0 1
180 1 0 1
0 1 0 1.5
0 1 0 1.5
Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (Speaker boost enabled) Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (OUT3 and OUT4 boost enabled) Stereo playback to OUT3/OUT4 (DACs input to OUT3/OUT4 mixers via left/right mixers) Differential output of right bypass path via OUT3/OUT4 (Phase shown relative to right bypass) Differential output of mono mix of DACs via LOUT2/ROUT2 (e.g. BTL speaker drive) High power speaker drive
0
0
0
1
0
0
0 1
0
0
0
0
1
1
180 1.5
180 1.5
0 1
0 1
180 1
180 1
0
0
0
0
0
0
LDAC2OUT3=0 RDAC2OUT4=0 LMIX2OUT3=1 RMIX2OUT4=1 BYPR2OUT4=1 OUT4_2OUT3=1
180 1
180 1
0 1
0 1
180 1
180 1
0
0
0
0
0
0
180 1
0 1
X
X
X
X
0
0
1
0
0
0
0 1
0 1 0 1
0 1 0 1
0 1 0 1
180 1 0 1.5
0 1 180 1.5
0
0
1
1
0
0
0 1
Table 41 Relative Output Phases Note that differential output should not be set up by combining outputs in boost mode with outputs which are not in boost mode as this would cause a DC offset current on the outputs.
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ENABLING THE OUTPUTS
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Each analogue output of the WM8983 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of the WM8983 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see "Power Management" and "Applications Information" sections). REGISTER ADDRESS R1 Power Management 1 R2 Power Management 2 R3 Power Management 3 BIT 2 6 7 8 8 7 6 LABEL BUFIOEN OUT3MIXEN OUT4MIXEN BUFDCOPEN ROUT1EN LOUT1EN SLEEP DEFAULT 0 0 0 0 0 0 0 DESCRIPTION Unused input/output bias buffer enable OUT3 mixer enable OUT4 mixer enable Output stage 1.5xAVDD/2 driver enable ROUT1 output enable LOUT1 output enable 0 = Normal device operation 1 = Supply current reduced in device standby mode Left mixer enable Right mixer enable ROUT2 output enable LOUT2 output enable OUT3 enable OUT4 enable 2nd enable bit for L/ROUT1 2 stage enable for L/ROUT1
2 3 5 6 7 8
LMIXEN RMIXEN ROUT2EN LOUT2EN OUT3EN OUT4EN DELEN OUT1DEL
0 0 0 0 0 0 0 0
R42 Output ctrl1
1 0
Note: All "Enable" bits are 1 = ON, 0 = OFF Table 42 Output Stages Power Management Control OUT1DEL and OUT2DEL enable lower pop noise power-up option. See start-up sequences. (in 2 stage enable method, normal enable bit is set, followed shortly later by the delayed enable DELEN)
THERMAL SHUTDOWN
To protect the WM8983 from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 1250C and the thermal shutdown circuit is enabled (TSDEN=1) the L/ROUT2 amplifiers will be disabled. The thermal shutdown may also be configured to generate an interrupt. See the GPIO and Interrupt Controller section for details. REGISTER ADDRESS R49 Output Control BIT 1 LABEL TSDEN DEFAULT 0 DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 43 Thermal Shutdown
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WM8983
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (either AVDD1/2 or 1.5xAVDD1/2 as appropriate) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k. REGISTER ADDRESS R49 BIT 0 LABEL VROI DEFAULT 0 DESCRIPTION VREF (AVDD1/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k
Table 44 Disabled Outputs to VREF Resistance A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 34. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled. Figure 34 summarises the bias options for the output pins.
Figure 34 Unused Input/Output Pin Tie-off Buffers
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L/ROUT2EN/ OUT3/4EN 0 0 0 0 1 1 OUT3BOOST/ OUT4BOOST/ SPKBOOST 0 0 1 1 0 1 VROI
Product Preview OUTPUT CONFIGURATION
0 1 0 1 X X
1k tie-off to AVDD1/2 30k tie-off to AVDD1/2 1k tie-off to 1.5xAVDD1/2 30k tie-off to 1.5xAVDD1/2 Output enabled (DC level=AVDD1/2) Output enabled (DC level=1.5xAVDD1/2)
Table 45 Unused Output Pin Bias Options
DIGITAL AUDIO INTERFACES
The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8983 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: * * * * * Left justified Right justified I 2S DSP mode early DSP mode late
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8983 audio interface may be configured as either master or slave. As a master interface device the WM8983 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8983 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 35 Left Justified Audio Interface (assuming n-bit word length)
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WM8983
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
Figure 36 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 37 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the LRC pulse shown in Figure 38 and Figure 39. In device slave mode, Figure 40 and Figure 41, it is possible to use any length of LRC pulse less than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the rising edge of the next LRC pulse.
Figure 38 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
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Figure 39 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
Figure 40 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 41 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)
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Product Preview REGISTER ADDRESS R4 Audio Interface Control BIT 0 LABEL MONO DEFAULT 0 DESCRIPTION
WM8983
Selects between stereo and mono device operation: 0 = Stereo device operation 1 = Mono device operation. Data appears in `left' phase of LRC. Controls whether ADC data appears in `right' or `left' phases of LRC clock: 0=ADC left data appear in `left' phase of LRC and right data in 'right' phase 1=ADC left data appear in `right' phase of LRC and right data in 'left' phase Controls whether DAC data appears in `right' or `left' phases of LRC clock: 0=DAC left data appear in `left' phase of LRC and right data in 'right' phase 1=DAC left data appear in `right' phase of LRC and right data in 'left' phase Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) LRC clock polarity 0=normal 1=inverted BCLK polarity 0=normal 1=inverted Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input.
1
ADCLRSWAP
0
2
DACLRSWAP
0
4:3
FMT
10
6:5
WL
10
7
LRP
0
8
BCP
0
R5
0
LOOPBACK
0
Table 46 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK and LRC are outputs. The frequencies of BCLK and LRC in master mode are controlled using MCLKDIV; these clocks are divided down versions of PLL output clock (SYSCLK). The MCLKDIV default setting provides a SYSCLK/256 division rate for the LRC output clock. It is possible to divide down the BCLK rate using BCLKDIV; care must be taken in choosing the correct BCLKDIV rate to maintain sufficient BCLK pulses per LRC period for the chosen data word length. The BCLKDIV default setting provides a BCLK = SYSCLK clock.
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REGISTER ADDRESS R6 Clock Generation Control BIT 0 MS LABEL DEFAULT 0
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DESCRIPTION Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs (Slave mode) 1=BCLK and LRC clock are outputs generated by the WM8983 (Master mode) Configures the BCLK and LRC output frequency, for use when the chip is in Master mode. 000=divide by 1 (BCLK=SYSCLK) 001=divide by 2 (BCLK=SYSCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the division for either the MCLK or PLL clock output (selected by CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 (LRC=SYSCLK/256) 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 47 Clock Control
SAMPLE RATE (KHZ) 8 11.025 12 16 22.05 24 32 44.1 48
SYSCLK (MHZ) (256FS CLOCK) 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 11.2896 12.288
MCLKDIV R6 [BIT 7:5] 111 = divide by 12 110 = divide by 8 110 = divide by 8 101 = divide by 6 100 = divide by 4 100 = divide by 4 011 = divide by 3 010 = divide by 2 010 = divide by 2
SR R7 [BIT3:1] 010 100 100 011 010 010 001 000 000
Table 48 Register Settings and Required SYSCLK for Common Sample Rates
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WM8983
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8983 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
REGISTER ADDRESS R5 Companding Control
BIT 2:1
LABEL ADC_COMP
DEFAULT 0
DESCRIPTION ADC companding 00 = off 01 = reserved 10 = -law 11 = A-law DAC companding 00 = off 01 = reserved 10 = -law 11 = A-law 0 = off 1 = device operates in 8-bit mode.
4:3
DAC_COMP
0
5
WL8
0
Table 49 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x } for 1/A 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK's per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK's and can be used with 8-bit data words using the A-law and u-law companding functions.
BIT8 SIGN
BIT[7:4] EXPONENT
BIT[3:0] MANTISSA
Table 50 8-bit Companded Word Composition
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u-law Companding
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1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 42 -Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 43 A-Law Companding
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WM8983
AUDIO SAMPLE RATES
The WM8983 filter characteristics for the ADCs and the DACs are set using the SR register bits; these bits do not change the rate of the audio interface output clocks in Master mode. The cut-offs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate is required which is not explicitly supported by the SR register settings, then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
REGISTER ADDRESS R7 Additional Control
BIT 3:1
LABEL SR
DEFAULT 000
DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110-111 = reserved
Table 51 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8983 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8983 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from an existing audio master clock. Figure 44 shows the PLL and internal clocking on the WM8983. The PLL can be enabled or disabled by the PLLEN register bit.
REGISTER ADDRESS R1 Power management 1
BIT 5
LABEL PLLEN
DEFAULT 0 PLL enable 0 = PLL off 1 = PLL on
DESCRIPTION
Table 52 PLLEN Control Bit
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Figure 44 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 44) can be set using the register bits PLLK and PLLN. R should be chosen to ensure 5 < PLLN < 13: PLLN = int R PLLK = int (224 (R-PLLN))
To calculate R: There is a fixed divide by 4 in the PLL, f/4, and a selectable divide by N after the PLL, MCLKDIV. * * * * f2 = SYSCLK x 4 x MCLKDIV R = f2 / (MCLK / PRESCALE) = R PLLN = int R k = int ( 224 x (R - intR)) - convert k to hex for PLLK
EXAMPLE: MCLK=26MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. MCLKDIV = 2 sets the required division rate; SYSCLK/256. * * * * f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / (26/2) = 7.561846 PLLN = int R = 7 k = int ( 2
24
x (7.561846 - 7)) = 9426214dec
Convert k to hex: PLLK = 8FD526h Convert PLLK to R36, R37, R38 and R39 hex values: R36 = 7h; R37 = 23h; R38 = 1EAh; R39 = 126h
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WM8983
REGISTER ADDRESS R36 PLL N value BIT 4 3:0 LABEL PLLPRESCALE PLLN DEFAULT 0 1000 DESCRIPTION Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0
PLLK [23:18]
0Ch
8:0
PLLK [17:9]
093h
8:0
PLLK [8:0]
0E9h
Table 53 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 54.
MCLK (MHz) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27
DESIRED OUTPUT (MHz) 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288
F2 (MHz)
PRESCALE DIVIDE
MCLKDIV
R
PLLN R36 (Hex)
K (Hex)
PLLK [23:18] R37 (Hex)
PLLK [17:9] R38 (Hex) 161 93 145 1EA D0 1D0 39 B8 DA C0 1BB 100 161 93 145 1EA 56 11
PLLK [8:0] R39 (Hex) 26 E9 1D4 126 1CA 6D B0 A3 92 9F F8 9E 26 E9 1D4 126 94 96
90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304
1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7
86C226 3126E8 F28BD4 8FD525 45A1CA D3A06E 6872AF 3D70A3 2DB492 FD809F 1F76F7 EE009E 86C226 3126E8 F28BD4 8FD525 BOAC93 482296
21 C 3C 23 11 34 1A F B 3F 7 3B 21 C 3C 23 2C 12
Table 54 PLL Frequency Examples for Common MCLK Rates
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GENERAL PURPOSE INPUT/OUTPUT
The WM8983 has three dual purpose input/output pins. * * * CSB/GPIO1: CSB / GPIO1 pin L2/GPIO2: Left channel line input / headphone detection input R2/GPIO3: Right channel line input / headphone detection input
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The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 and GPIO2 functions are provided for use as jack detection inputs or general purpose outputs. The default configuration for the CSB/GPIO1 is to be an input. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. Table 55 illustrates the functionality of the GPIO1 pin when used as a general purpose output.
REGISTER ADDRESS R8 GPIO Control
BIT 2:0
LABEL GPIO1SEL
DEFAULT 000
DESCRIPTION CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1 GPIO1 Polarity invert 0 = Non inverted 1 = Inverted PLL Output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4
3
GPIO1POL
0
5:4
OPCLKDIV
00
Table 55 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the GPIO1SEL[2:0] bits. For further details of the jack detect operation see the OUTPUT SWITCHING section.
OUTPUT SWITCHING (JACK DETECT)
When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and R2/GPIO3 pins can also be used for this purpose. The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK. Note that the GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is used. The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signals which are used if the selected jack detection pin is at logic 0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).
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WM8983
Similar to the output enables, VMID can be output to OUT3. This VMID output can be configured to be on/off depending on the jack detection input polarity of VMID_EN_0 and VMID_EN_1. The jack detection enables operate as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 42). When an output is normally enabled at per Table 42, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due to the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000. The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings. If jack detection is not enabled (JD_EN=0), the output enables default to all 1's, allowing the outputs to be controlled as normal via the normal output enables found in Table 42. Similarly the VMID_EN signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit. BIT REGISTER ADDRESS R9 GPIO control 5:4 JD_SEL 00 Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved Jack Detection Enable 0 = disabled 1 = enabled [7] VMID_EN_0 [8] VMID_EN_1 Output enables when selected jack detection input is logic 0. 0000 = OUT1_EN_0 0001 = OUT2_EN_0 0010 = OUT3_EN_0 0011 = OUT4_EN_0 0100-1111 = Reserved Output enables when selected jack detection input is logic 1 0000-0011 = Reserved 0100 = OUT1_EN_1 0101 = OUT2_EN_1 0110 = OUT3_EN_1 0111 = OUT4_EN_1 1000-1111 = Reserved LABEL DEFAULT DESCRIPTION
6
JD_EN
0
8:7 R13 3:0
JD_VMID JD_EN0
00 0000
7:4
JD_EN1
0000
Table 56 Jack Detect Register Control Bits
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CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
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The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 57. The WM8983 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are register address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 data bits in each control register. MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 57 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 45 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8983 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8983). The WM8983 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8983, the WM8983 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8983 returns to the idle condition and waits for a new start condition and valid address. During a write, once the WM8983 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8983 register address plus the first bit of register data). The WM8983 then acknowledges the first data byte by driving SDIN low for one clock cycle. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8983 acknowledges again by pulling SDIN low. Transfer is complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8983 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the control interface returns to the idle condition.
SDIN
DEVICE ADDRESS (7 BITS)
RD / WR BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 7 TO 0)
ACK (LOW)
SCLK
START
register address and 1st register data bit
remaining 8 bits of register data
STOP
Figure 46 2-Wire Serial Control Interface
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Product Preview In 2-wire mode the WM8983 has a fixed device address, 0011010.
WM8983
RESETTING THE CHIP
The WM8983 can be reset by performing a write of any value to the software reset register (address 0h). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the device is powered up.
POWER SUPPLIES
The WM8983 requires four separate power supplies: AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1 and ROUT1. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones). Higher AVDD1 will improve audio quality. AVDD2 and AGND2: Output driver supplies, power LOUT2, ROUT2, OUT3 and OUT4. AVDD2 must be between 2.5V and 5.5V. AVDD2 can be tied to AVDD1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD must be between 1.71V and 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths.
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 and DACOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS R10 DAC control R14 ADC control 3 BIT LABEL DACOSR128 DEFAULT 0 DESCRIPTION DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
3
ADCOSR128
0
Table 58 ADC and DAC Oversampling Rate Selection
VMID
The analogue cicruitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS R1 Power management 1 BIT 1:0 LABEL VMIDSEL DEFAULT 00 DESCRIPTION Reference string impedance to VMID pin (Determines startup time): 00 = off (250k VMID to AGND1) 01 = 100k total, 25k impedance 10 = 500k total, 125k impedance 11 = 10k total, 2.5k impedance
Table 59 VMID Impedance Control
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WM8983
BIASEN
The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS R1 Power management 1 BIT 3 LABEL BIASEN DEFAULT 0
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DESCRIPTION Analogue amplifier bias control 0 = disabled 1 = enabled
Table 60 Analogue Bias Control
BIAS CONTROL
Control of the analog bias values is possible using register 61 and 62 REGISTER ADDRESS R61 Bias control BIT 8 LABEL BIASCUT DEFAULT 0 DESCRIPTION Global bias control 0 = normal 1 = 0.5x Input bias control 0 = normal 1 = 0.5x ADC input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x ADC input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x Output bias 0 = normal 1 = 0.5x DAC bias 0 = normal 1 = 0.5x
6
HALF_ IPGA BUFBIAS
0
4,3
01
2,1
ADCBIAS
01
0
HALFOP BIAS HALF DACI
0
R62
3
0
Table 61 Analogue Bias Control Note that these bits must be used with care and may cause degradation in analog performance. For example, if both BIASCUT and HALFDACI are used at same time, the playback THD will be poor.
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WM8983
REGISTER MAP
ADDR B[15:9] D E C 0 1 2 3 4 5 6 7 H E X 00 01 02 03 04 05 06 07 Software Reset Power manage't 1 Power manage't 2 Power manage't 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl BUFDC OPEN ROUT1 EN OUT4EN BCP 0 CLKSEL 0 0 OUT4 MIXEN LOUT1 EN OUT3EN LRP 0 0 MCLKDIV 0 0 0 OUT3 MIXEN SLEEP LOUT2 EN WL WL8 PLLEN BOOST ENR ROUT2 EN Software reset MICBEN BOOST ENL 0 BIASEN INPGA ENR RMIXEN FMT DAC_COMP BCLKDIV SR BUFIO EN INPPGA ENL LMIXEN DLR SWAP VMIDSEL ADC ENR DAC ENR ALR SWAP ADC ENL DAC ENL MONO LOOP BACK MS SLOWC LK EN GPIO1SEL[2:0] 0 AMUTE 0 DACR POL 0 DACL POL 000 000 000 050 000 140 000 REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF'T VAL
(HEX)
ADC_COMP 0
8 9 10 11 12 13 14 15 16 18 19 20 21 22 24 25 27 28 29 30 32 33 34
08 09 0A 0B 0C 0D 0E 0F 10 12 13 14 15 16 18 19 1B 1C 1D 1E 20 21 22
GPIO Stuff Jack detect control DAC Control Left DAC digital Vol Right DAC dig'l Vol Jack Detect Control ADC Control Left ADC Digital Vol Right ADC Digital Vol EQ1 - low shelf EQ2 - peak 1 EQ3 - peak 2 EQ4 - peak 3 EQ5 - high shelf DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3
0 JD_VMID 1 0 DACVU DACVU 0 HPFEN ADCVU ADCVU EQ3D MODE EQ2BW EQ3BW EQ4BW 0 LIMEN 0 NFU NFU NFU NFU ALCSEL ALCZC ALC MODE
0 JD_VMI D0 0
0 JD_EN SOFT MUTE
OPCLKDIV JD_SEL 0 0
GPIO1P OL 0 DAC OSR128 DACLVOL DACRVOL
000 000 000 0FF 0FF
JD_EN1 HPFAPP HPFCUT ADC OSR128 ADCLVOL ADCRVOL 0 0 0 0 0 0 NFEN 0 0 0 0 ALCHLD ALCDCY ALCMAX EQ1C EQ2C EQ3C EQ4C EQ5C LIMDCY LIMLVL NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] 0
JD_EN0 ADCR POL ADC LPOL
000 100 0FF 0FF
EQ1G EQ2G EQ3G EQ4G EQ5G LIMATK LIMBOOST
12C 02C 02C 02C 02C 032 000 000 000 000 000 ALCMIN 038 00B 032
ALCLVL ALCATK
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WM8983
ADDR B[15:9] D E C 35 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 61 H E X 23 24 25 26 27 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3D Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 3D control OUT4 to ADC Beep control Input ctrl Left INP PGA gain ctrl Right INP PGA gain ctrl Left ADC Boost ctrl Right ADC Boost ctrl Output ctrl Left mixer ctrl Right mixer ctrl LOUT1 (HP) volume ctrl ROUT1 (HP) volume ctrl LOUT2 (SPK) volume ctrl ROUT2 (SPK) volume ctrl OUT3 mixer ctrl OUT4 (MONO) mixer ctrl Bias Control OUT1VU OUT1VU OUT2VU OUT2VU 0 0 BIASCUT BYPL2 RMIX MICBV SEL INPGAVU INPGAVU PGA BOOSTL PGA BOOSTR 0 OUT4_2ADCVOL BYPR2 LMIX 0 INPPGA ZCL INPPGA ZCR 0 0 0 AUXLMIXVOL AUXRMIXVOL LOUT1 ZC ROUT1 ZC LOUT2 ZC ROUT2 ZC 0 OUT3_2 OUT4 0 LOUT1 MUTE ROUT1 MUTE LOUT2 MUTE ROUT2 MUTE OUT3 MUTE OUT4 MUTE HALF I_IPGA 0 OUT4 ATTN 0 0 LMIX2 OUT4 DACL2 RMIX 0 R2_2 INPPGA INPPGA MUTEL INPPGA MUTER L2_2BOOSTVOL R2_2BOOSTVOL DACR2 LMIX AUXL2 LMIX AUXR2 RMIX OUT4 BOOST OUT4_2 LNR 0 RIN2 INPPGA 0 0 RIP2 INPPGA 0 0 0 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] DEPTH3D POB CTRL 0 L2_2 INPPGA DELEN 0 LIN2 INPPGA 0 0 0 PLLPRE SCALE PLLK[23:18] NGEN NGTH PLLN[3:0] REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1
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(HEX) 000 008 00C 093 0E9 000 OUT1 DEL 0 LIP2 INPPGA 000 003 010 010 AUXL2BOOSTVOL AUXR2BOOSTVOL SPK BOOST TSDEN BYPL2 LMIX BYPR2 RMIX VROI DACL2 LMIX DACR2 RMIX 100 100 002 001 001 039 039 039 039 LMIX2 OUT3 RMIX2 OUT4 LDAC2 OUT3 RDAC2 OUT4 HALF OPBIAS 001 001 000
INPPGAVOLL INPPGAVOLR 0 0 OUT3 BOOST BYPLMIXVOL BYPRMIXVOL LOUT1VOL ROUT1VOL LOUT2VOL ROUT2VOL OUT4_ 2OUT3 LDAC2 OUT4 BYPL2 OUT3 BYPR2 OUT4
BUFBIAS[1:0]
ADCBIAS[1:0]
Table 62 WM8983 Register Map
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WM8983
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 63 Digital Filter Characteristics f > 0.546fs 0.546fs -80 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
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WM8983
DAC FILTER RESPONSES
0.2
0
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0.15
-20 Response (dB) -40 -60 -80 -100
0.1 Response (dB)
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
0.05 0 -0.05 -0.1 -0.15
-120
-0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 47 DAC Digital Filter Frequency Response
Figure 48 DAC Digital Filter Ripple
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
Response (dB)
0.15 0.1 0.05 0 -0.05 -0.1
-40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 49 ADC Digital Filter Frequency Response
Figure 50 ADC Digital Filter Ripple
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WM8983
HIGHPASS FILTER
The WM8983 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cut-off frequency.
5 0 -5 -10 Response (dB) -15 -20 -25 -30 -35 -40 0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
Figure 51 ADC Highpass Filter Response, HPFAPP=0
10 0 -10
10 0 -10 -20
Response (dB)
-20 -30 -40
Response (dB)
-30 -40 -50 -60
-50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 52 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cut-off settings shown.
Figure 53 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cut-off settings shown.
10 0 -10 -20 Response (dB) -30 -40 -50 -60 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 54 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cut-off settings shown.
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WM8983
5-BAND EQUALISER
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The WM8983 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 55 to Figure 68 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 55 EQ Band 1 Low Frequency Shelf Filter Cut-offs
Figure 56 EQ Band 1 Gains for Lowest Cut-off Frequency
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 57 EQ Band 2 - Peak Filter Centre Frequencies, EQ2BW=0
15
Figure 58
EQ Band 2 - Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 59 EQ Band 2 - EQ2BW=0, EQ2BW=1
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WM8983
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 60 EQ Band 3 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 61
EQ Band 3 - Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 62 EQ Band 3 - EQ3BW=0, EQ3BW=1
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WM8983
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15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 63 EQ Band 4 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 64
EQ Band 4 - Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 65 EQ Band 4 - EQ3BW=0, EQ3BW=1
15 15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 66 EQ Band 5 High Frequency Shelf Filter Cut-offs
Figure 67 EQ Band 5 Gains for Lowest Cut-off Frequency
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Product Preview
WM8983
Figure 68 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.
20
15
10
Magnitude (dB)
5
0
-5
-10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 68 Cumulative Frequency Boost/Cut
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WM8983 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
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Figure 69 External Component Diagram
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WM8983
PACKAGE DIAGRAM
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM030.E
CORNER TIE BAR 5 25
D2 B D2/2 32
SEE DETAIL A
D
L 24 EXPOSED GROUND 6 PADDLE A 1 INDEX AREA (D/2 X E/2) E2/2
E2
SEE DETAIL B
E
17
8 2X 16 e 15 B 9 b 2X aaa C aaa C
BOTTOM VIEW
ccc C (A3) 1 A 0.08 C bbb M C A B 1
TOP VIEW
DETAIL A
32x b
CORNER TIE BAR 5
C
SIDE VIEW
SEATING PLANE
1 e/2 TERMINAL TIP
A1
L
0. 43 m m 0.5
32x K
DETAIL B
DATUM
66 m m
EXPOSED GROUND PADDLE
R
1 L1
e
Symbols A A1 A3 b D D2 E E2 e L L1 R K aaa bbb ccc REF: MIN 0.85 0 0.18 4.90 3.2 4.90 3.2 0.35
1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2
Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 5.10 3.3 3.4 5.00 5.10 3.3 3.4 0.5 BSC 0.4 0.45 0.1
L1
R
NOTE
1 2 2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
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WM8983 IMPORTANT NOTICE
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Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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